This invention relates to digital speech synthesis circuits capable of being implemented on an integrated circuit device, and, more specifically, to digital-to-analog converter circuitry suitable for such speech synthesis circuits.
Several techniques are known in the prior art for digitizing human speech. For example, pulse code modulation, differential pulse code modulation, adaptive predictive coding, delta modulation, channel vocoders, cepstrum vocoders, formant vocoders, voice excited vocoders, and linear predictive coding techniques of speech digitization are known. The techniques are briefly explained in "Voice Signals; Bit by Bit" on pages 28-34 of the Oct., 1973 issue of IEEE Spectrum.
In certain applications and particularly those in which digitized speech is to be stored in a memory, most researchers tend to use the linear predictive coding technique because it produces a very high quality speech using rather low data rates. An excellent example of the use of linear predictive coding systems, implementable in integrated circuit techniques may be seen in U.S. Patent Application Ser. No. 901,393, filed Apr. 28, 1978, now U.S. Pat. No. 4,209,836 issued June 24, 1980. The speech synthesis system described in the aforementioned U.S. Pat. No. 4,209,836 utilizes frames of data which are comprised of digital representations of pitch, energy and certain linear predictive coefficients which are utilized to control a digital filter. The system described in the aforementioned U.S. Pat. No. 4,209,836 is capable of producing high quality synthetic human speech at a bit rate of as low as 1200 bits per second, utilizing a fixed rate of data frame entry. A problem encountered in integrated circuit speech synthesis circuitry involves the conversion of digital signals into analog signals with sufficient accuracy to generate analog signals representative of human speech. While certain large values of speech signals may be clipped or truncated, accurate portrayal of small values in the speech waveform is necessary to synthesize human speech accurately. Standard digital-to-analog conversion techniques such as disclosed in U.S. Pat. No. 4,209,836, while adequate for higher voltage PMOS implementation lack sufficient accuracy and resolution for lower voltage applications such as CMOS circuitry. A lower voltage application such as CMOS circuitry prohibits the large voltage swing necessary to implement standard digital-to-analog converter circuitry.
It is therefore one object of this invention to improve speech synthesis technology.
It is another object of this invention to provide a digital-to-analog converter capable of accurately converting digital data into analog signals representative of human speech.
It is still another object of this invention to provide a digital-to-analog converter circuit capable of accurately converting digital data into analog signals representative of human speech, while operating at lower voltage levels.
The foregoing objects are achieved as is now described. A digitally programmable shift register is utilized to generate a pulse, which is generally related to the magnitude of a digital signal. A programmable delay circuit provides finer resolution by converting the least significant digital bits of data into pulse width information of shorter duration than the minimum pulse width generated by the controllable shift register. Pulse width information generated by the shift register and delay circuit is applied to the bases of two crossconnected transistors to drive a speaker or voice coil.